Please use this identifier to cite or link to this item: http://hdl.handle.net/20.500.12696/3653
Title: Diseño de arquitecturas para la mitigación de fallos hardware en procesadores multinúcleo = Microarchitectural approaches for hardware fault mitigation in multicore processors
Issue Date: 29-Nov-2011
metadata.dc.date.created: 25-Jul-2011
Authors: Sánchez Pedreño, Daniel
metadata.dc.contributor.advisor: Aragón Alcaraz, Juan Luis
García Carrasco, José Manuel
metadata.dc.contributor.other: Departamento de Ingeniería y Tecnología de Computadores
URI: http://hdl.handle.net/20.500.12696/3653
metadata.dc.type: info:eu-repo/semantics/doctoralThesis
metadata.dc.rights: info:eu-repo/semantics/closedAccess
Appears in Collections:Tesis Inéditas

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